Video 1Duration 12:43
Design Optimization
Measure, optimize, and verify an RTL divider.
- 0:22Tour the PicoRV32 divider
- 1:13Simulate Dhrystone with tracing
- 2:52Show the divider in the waveform viewer
- 4:50Measure latency with bwave: 34 cycles
- 6:11Synthesize a baseline: 3.1 kGE
- 7:09Choose radix-4 plus early exit
- 9:15Implement, re-test, and re-measure
- 10:26Results: up to 15× faster, +77% area