Application notes¶

I asked an AI coding agent to fix a bug in the RISC-VAn open instruction set architecture. Many open-source processor cores implement it. processor inside CaliptraA large open-source system on chip from CHIPS Alliance. It is a hardware root of trust: a security block with its own RISC-V processor and firmware.. It usually found the faulty line of RTLRegister-transfer level: the code that describes a chip’s hardware, usually written in Verilog or SystemVerilog. A simulator runs it; synthesis tools turn it into gates. within five minutes. Proving the fix took much longer, because the agent first had to make the bug show up in simulation. Over ten trials, two hardware-specific problems took most of that time: the internal signals that explain a failure are invisible unless the simulation records them, and simulations run long enough that the agent has to guess when they finish. A third problem, a build that depends on settings the agent's shell doesn't keep, isn't specific to hardware but is common in RTL projects. With tools aimed at all three, the same agent's mean time to a verified fix fell from 56 minutes to 21.