Evaluation designs
Open-source designs already set up for Booley. Clone one, open it in VS Code, and give the agent a task. They are examples, not the only designs Booley supports: you can set up any RTL project the same way.
1Available designs
Table 1. Open-source designs already set up for Booley
| Design | What it is | Notes | Booley project |
|---|---|---|---|
| PicoRV32 | A small RISC-V CPU core (YosysHQ/picorv32) | Start here. Clone it, open it in VS Code, and type your first request to the agent. | Open the PicoRV32 demo |
| Caliptra1 | The open-source hardware root of trust (chipsalliance/caliptra-rtl): a full SoC with a RISC-V core and firmware | Real large codebase. Caliptra’s Verilator testbench, firmware tests, lint, and ASIC synthesis are wired into Booley Flows, so the agent can simulate the whole SoC and inspect its waveforms. | Open the Caliptra project |
- 1. Caliptra’s Sandbox uses the RISC-V image and asks for 28 GB of memory.
Using your own design. Booley is not limited to the designs in Table 1. Run booley init in your own RTL repository, then let the booley-setup skill plan and configure the project with you. Starting a new IP from scratch? booley init --scaffold writes a working starter project. See the setup guide.
2Typical procedure
Running your own change on a demo
- Clone the configured demo project from Table 1.
- Open it in VS Code.
- Type a request to the agent, such as your own change to the design.
Booley must be installed first: pipx install booley-rtl, then booley bootstrap. See the installation guide.
3See it run
Two video walkthroughs show an engineer driving Booley on a demo project, start to finish.